1. Field of the Invention
The present invention relates to a design structure for a digital switching of clock signals in a computer system, and in particular to a design structure for switching signals with clock logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks.
2. Description of the Related Art
Clocks are periodic signals used for timing alignment and synchronization in an integrated circuit device (also called a chip). With the recent system large scale integration (LSI), a chip will commonly have clocks comprising multiple frequencies. Clock selection from multiple clock sources is often used to implement several operation modes, such as high performance mode, low power mode, test evaluation mode, etc. When implementing clock selection, it is necessary to switch the source of the clock line while the chip is running. One method of switching the source of a clock line is through the use of a multiplexer. A multiplexer is a device that selects one input signal source from several input signal sources and passes that signal to the output.
One problem that can occur during a switch is that a glitch may be generated on the clock line. A glitch on the clock line occurs when the switching timing is not properly controlled during the switch, which can cause data integrity problems. A glitchless clock multiplexer (GM) is typically used for clock selection to prevent the occurrence of glitches in multiplexer outputs. However, eliminating glitches in the clock line can be difficult if the clock sources are totally asynchronous and the required switching latency is very short. The switching latency is the time required for a multiplexer to switch from one input clock signal to another input clock signal. If the input clock sources include clocks which are categorized into both synchronous clock groups and asynchronous clock groups, it is much harder to optimize the performance of the glitchless clock multiplexer while keeping the switching latency at a minimum.